US 12,001,280 B2
Overcoming error correction coding mis-corrects in non-volatile memory
Krishna K. Parat, Palo Alto, CA (US); Ravi H. Motwani, Fremont, CA (US); Rohit S. Shenoy, Fremont, CA (US); and Ali Khakifirooz, Brookline, MA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 24, 2020, as Appl. No. 17/133,995.
Prior Publication US 2021/0117270 A1, Apr. 22, 2021
Int. Cl. G06F 11/00 (2006.01); G06F 11/10 (2006.01); G11C 11/56 (2006.01); G11C 16/26 (2006.01); G11C 16/04 (2006.01)
CPC G06F 11/1068 (2013.01) [G11C 11/5621 (2013.01); G11C 16/26 (2013.01); G11C 16/0483 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A memory controller comprising:
a read logic to apply a read voltage shift to a read reference voltage level in advance of a read of a page of non-volatile memory cells encoded to store multiple pages;
an error correction coding (ECC) logic to verify that the read of the page was correct;
a mis-correct logic to detect silent data corruption in a non-volatile memory device in which the page is located, including to determine whether the read of the page verified as correct is instead an ECC mis-correct; and
wherein the ECC mis-correct is determined based on a read signature of a result of the read that indicates the result includes data from a different page.