US 12,001,279 B2
Error protection for managed memory devices
Chandrakanth Rapalli, Hyderabad (IN); Yoav Weinberg, Toronto (CA); and Tal Sharifie, Lehavim (IL)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Oct. 20, 2022, as Appl. No. 18/048,284.
Prior Publication US 2024/0134740 A1, Apr. 25, 2024
Int. Cl. G06F 11/10 (2006.01); H03M 13/00 (2006.01); H03M 13/09 (2006.01)
CPC G06F 11/1004 (2013.01) [H03M 13/095 (2013.01); H03M 13/611 (2013.01); G06F 11/1008 (2013.01)] 25 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a controller associated with a memory device, wherein the controller is configured to cause the apparatus to:
obtain a plurality of protocol units associated with a data block, wherein each protocol unit of the plurality of protocol units comprises a set of first data and a respective first set of parity bits;
process a first subset of the plurality of protocol units to obtain a first data storage unit based on respective first sets of parity bits matching respective second sets of parity bits generated from respective sets of first data for the first subset of the plurality of protocol units, wherein the first data storage unit comprises the data block and a check code generated from the data block; and
transmit a plurality of first codewords to a memory array of a memory system, wherein the plurality of first codewords comprise the data block and the check code, and wherein each first codeword comprises a first error protection code associated with a first error protection scheme.