CPC G06F 11/1004 (2013.01) [H03M 13/095 (2013.01); H03M 13/611 (2013.01); G06F 11/1008 (2013.01)] | 25 Claims |
1. An apparatus, comprising:
a controller associated with a memory device, wherein the controller is configured to cause the apparatus to:
obtain a plurality of protocol units associated with a data block, wherein each protocol unit of the plurality of protocol units comprises a set of first data and a respective first set of parity bits;
process a first subset of the plurality of protocol units to obtain a first data storage unit based on respective first sets of parity bits matching respective second sets of parity bits generated from respective sets of first data for the first subset of the plurality of protocol units, wherein the first data storage unit comprises the data block and a check code generated from the data block; and
transmit a plurality of first codewords to a memory array of a memory system, wherein the plurality of first codewords comprise the data block and the check code, and wherein each first codeword comprises a first error protection code associated with a first error protection scheme.
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