US 12,001,266 B1
Method and apparatus for managing power of ferroelectric or paraelectric logic and CMOS based logic
Amrita Mathuriya, Portland, OR (US); Christopher B. Wilkerson, Portland, OR (US); Rajeev Kumar Dokania, Beaverton, OR (US); Debo Olaosebikan, San Francisco, CA (US); and Sasikanth Manipatruni, Portland, OR (US)
Assigned to Kepler Computing Inc., San Francisco, CA (US)
Filed by Kepler Computing Inc., San Francisco, CA (US)
Filed on Aug. 20, 2021, as Appl. No. 17/408,323.
Application 17/408,323 is a continuation of application No. 17/396,585, filed on Aug. 6, 2021, granted, now 11,791,233.
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 1/32 (2019.01); G06F 1/329 (2019.01); G11C 5/04 (2006.01); G11C 11/00 (2006.01); H01L 25/16 (2023.01); G06N 20/00 (2019.01)
CPC G06F 1/329 (2013.01) [G11C 5/04 (2013.01); G11C 11/005 (2013.01); H01L 25/162 (2013.01); G06N 20/00 (2019.01); H01L 2224/16146 (2013.01); H01L 2224/16225 (2013.01); H01L 2924/1441 (2013.01)] 19 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a first logic block including a first circuitry having ferroelectric logic or paraelectric logic;
a second logic block including a second circuitry having CMOS based logic; and
a power management unit having a third circuitry which is coupled to the first circuitry and the second circuitry, wherein the third circuitry is to manage power of the first logic block and the second logic block,
wherein the power management unit is to compute a first throughput ratio of the first logic block, and wherein the power management unit is to compute a second throughput ratio of the second logic block,
wherein the ferroelectric logic or the paraelectric logic includes at least three capacitors with first terminals to receive inputs and second terminals that are directly coupled to a node, wherein at least one capacitor of the at least three capacitors includes non-linear polar material, wherein the ferroelectric logic or the paraelectric logic includes a reset mechanism coupled to the node, wherein the reset mechanism is operable to reset charge on the node in a reset phase separate from an evaluation phase of the inputs, wherein the first logic block and the second logic block have an overlapping functionality, and wherein the power management unit is operable to manage power of the overlapping functionality in the first logic block and the second logic block.