US 12,001,262 B2
Systems and methods for performing in-flight computations
Mark Alan Lovell, Lucas, TX (US); and Robert Michael Muchsel, Addison, TX (US)
Assigned to MAXIM INTEGRATED PRODUCTS, INC., San Jose, CA (US)
Filed by Maxim Integrated Products, Inc., San Jose, CA (US)
Filed on May 25, 2021, as Appl. No. 17/330,022.
Prior Publication US 2022/0382361 A1, Dec. 1, 2022
Int. Cl. G06F 1/26 (2006.01); G06F 1/32 (2019.01); G06F 1/3234 (2019.01); G06F 9/30 (2018.01); G06F 9/50 (2006.01); G06N 3/08 (2023.01)
CPC G06F 1/3234 (2013.01) [G06F 9/3001 (2013.01); G06F 9/30105 (2013.01); G06F 9/5016 (2013.01); G06N 3/08 (2013.01); G06F 2209/5011 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for reducing power consumption in machine learning hardware accelerators, the method comprising:
retrieving input data from a source memory;
using a compute cache to perform one or more arithmetic operations on the input data to obtain a result; and
transferring the result to a hardware accelerator that performs a convolution operation and generates an output without generating, storing, accessing, or retrieving intermediate data, thereby, reducing at least one of read operations or write operations, wherein the hardware accelerator is a separate circuit from the compute cache.