US 12,001,232 B2
Gain limiter
Mityu Mitev, Munich (DE)
Assigned to Dialog Semiconductor (UK) Limited, London (GB)
Filed by Dialog Semiconductor (UK) Limited, London (GB)
Filed on Oct. 15, 2021, as Appl. No. 17/502,560.
Prior Publication US 2023/0123393 A1, Apr. 20, 2023
Int. Cl. G05F 1/575 (2006.01)
CPC G05F 1/575 (2013.01) 16 Claims
OG exemplary drawing
 
1. A low dropout, LDO, regulator for generating an output voltage at an output node of the LDO regulator based on an input voltage received at an input node of the LDO regulator, the LDO regulator comprising:
a first amplifier stage;
a driver stage;
a second amplifier stage coupled between the driver stage and the output node;
a feedback stage coupled between the output node and the first amplifier stage; and
a gain limiter stage coupled between the first amplifier stage and the driver stage at an intermediate node for lowering a regulation loop gain of the LDO regulator,
wherein the gain limiter stage comprises first and second current mirrors,
wherein one branch of the first current mirror and one branch of the second current mirror are coupled to the intermediate node;
wherein the gain limiter stage further comprises a capacitive element coupled in parallel with a diode-connected switching element of the first current mirror; and
wherein a capacitance of the capacitive element is set such that a current of a diode-connected switching element of the second current mirror is partially or fully compensated at low frequency, and/or is not, or is less, compensated at 0 dB gain frequency.