US 12,000,892 B2
Device under test (DUT) measurement circuit having harmonic minimization
Charles Kasimer Sestok, IV, Dallas, TX (US); and David Patrick Magee, Allen, TX (US)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Jan. 31, 2022, as Appl. No. 17/589,779.
Claims priority of provisional application 63/153,508, filed on Feb. 25, 2021.
Prior Publication US 2022/0268838 A1, Aug. 25, 2022
Int. Cl. G01R 31/00 (2006.01); G01R 31/3167 (2006.01); G01R 31/319 (2006.01); H03M 1/06 (2006.01); H03M 1/10 (2006.01)
CPC G01R 31/31922 (2013.01) [G01R 31/3167 (2013.01); G01R 31/31924 (2013.01); H03M 1/0629 (2013.01); H03M 1/1071 (2013.01)] 23 Claims
OG exemplary drawing
 
1. A circuit comprising:
a driver circuit having a clock input, a first frequency control input, and a driver output, the driver output coupled to a device under test (DUT) terminal;
a DUT parameter circuit having a processing input, a second frequency control input, and a DUT parameter output, the processing input coupled to the DUT terminal; and
a control circuit having a first frequency control output and a second frequency control output, the first frequency control output coupled to the first frequency control input, and the second frequency control output coupled to the second frequency control input.