US 12,000,888 B2
Integrated circuit including test circuit and method of manufacturing the same
Changho Han, Hwaseong-si (KR); Mijeong Lim, Seoul (KR); Yuncheol Kim, Hwaseong-si (KR); and Kwanghun Oh, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Jul. 5, 2022, as Appl. No. 17/857,379.
Claims priority of application No. 10-2021-0106181 (KR), filed on Aug. 11, 2021.
Prior Publication US 2023/0049110 A1, Feb. 16, 2023
Int. Cl. G01R 31/317 (2006.01); G01R 31/30 (2006.01); G01R 31/3173 (2006.01); G01R 31/3177 (2006.01); G01R 31/3183 (2006.01); G01R 31/3185 (2006.01); H01L 21/66 (2006.01)
CPC G01R 31/31725 (2013.01) [G01R 31/3016 (2013.01); G01R 31/31715 (2013.01); G01R 31/31727 (2013.01); G01R 31/3173 (2013.01); G01R 31/3177 (2013.01); G01R 31/318314 (2013.01); H01L 22/34 (2013.01); G01R 31/318513 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An integrated circuit comprising:
first to nth metal layers vertically stacked on a substrate; and
a test circuit configured to output a test result signal according to a characteristic of each of the first to nth metal layers,
wherein the test circuit comprises:
first to nth test circuits configured to generate a plurality of clock signals, each clock signal of the plurality of clock signals having a frequency according to a characteristic of a corresponding metal layer among the first to nth metal layers, and
wherein n is a natural number,
wherein each of the first to nth test circuits comprises a first ring oscillator and a second ring oscillator,
wherein a frequency of a first clock signal output from the first ring oscillator and a frequency of a second clock signal output from the second ring oscillator are different from each other,
wherein the first ring oscillator comprises a plurality of inverters connected with each other using a first test pattern formed in a corresponding metal layer of the first to nth metal layers,
wherein the second ring oscillator comprises a plurality of inverters connected with each other using a second test pattern formed in the corresponding metal layer of the first to nth metal layers, and
wherein an extension length of the first test pattern and an extension length of the second test pattern are different from each other.