US 12,324,364 B2
Memory device and operating method thereof
Tung-Ying Lee, Hsinchu (TW); Shao-Ming Yu, Hsinchu County (TW); Kai-Tai Chang, Kaohsiung (TW); Hung-Li Chiang, Taipei (TW); and Yu-Sheng Chen, Taoyuan (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jun. 30, 2021, as Appl. No. 17/363,032.
Claims priority of provisional application 63/156,953, filed on Mar. 5, 2021.
Prior Publication US 2022/0285617 A1, Sep. 8, 2022
Int. Cl. H10N 70/20 (2023.01); G11C 13/00 (2006.01); H10B 63/00 (2023.01); H10N 70/00 (2023.01)
CPC H10N 70/841 (2023.02) [G11C 13/0069 (2013.01); H10B 63/80 (2023.02); H10N 70/882 (2023.02); H10N 70/8833 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a bottom electrode;
a first data storage layer, disposed on the bottom electrode and in contact with the bottom electrode;
a second data storage layer, disposed over the first data storage layer, wherein a material of the second data storage layer includes a transitional metal oxide;
an interfacial conductive layer, disposed between the first data storage layer and the second data storage layer; and
a top electrode, disposed over the second data storage layer.