US 12,324,362 B2
Phase-change memory device and method
Tung Ying Lee, Hsinchu (TW); Yu Chao Lin, Hsinchu (TW); and Shao-Ming Yu, Zhubei (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jan. 26, 2024, as Appl. No. 18/423,769.
Application 17/812,773 is a division of application No. 16/992,210, filed on Aug. 13, 2020, granted, now 11,411,180, issued on Aug. 9, 2022.
Application 18/423,769 is a continuation of application No. 17/812,773, filed on Jul. 15, 2022, granted, now 11,925,127.
Claims priority of provisional application 63/016,337, filed on Apr. 28, 2020.
Prior Publication US 2024/0164223 A1, May 16, 2024
Int. Cl. H10N 70/00 (2023.01)
CPC H10N 70/063 (2023.02) [H10N 70/021 (2023.02); H10N 70/841 (2023.02); H10N 70/8828 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
forming a bottom electrode on a conductive feature;
performing a first etching process on the bottom electrode;
forming a phase-change material (PCM) layer on the bottom electrode;
performing a second etching process on the PCM layer;
forming a dielectric layer over the conductive feature, wherein the dielectric layer laterally surrounds the bottom electrode and the PCM layer; and
forming a top electrode on the dielectric layer, wherein the top electrode protrudes into the dielectric layer to physically contact the PCM layer.