US 12,324,360 B2
Semiconductor structure and method of forming the same
Georgios Vellianitis, Heverlee (BE); Gerben Doornbos, Kessel-Lo (BE); Marcus Johannes Henricus Van Dal, Linden (BE); and Mauricio Manfrini, Hsinchu County (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jul. 20, 2023, as Appl. No. 18/356,168.
Application 18/356,168 is a continuation of application No. 16/933,914, filed on Jul. 20, 2020, granted, now 11,751,487.
Prior Publication US 2023/0363291 A1, Nov. 9, 2023
Int. Cl. H10N 52/80 (2023.01); H10B 61/00 (2023.01); H10N 50/85 (2023.01); H10N 52/00 (2023.01); H10N 52/01 (2023.01)
CPC H10N 52/80 (2023.02) [H10B 61/10 (2023.02); H10N 50/85 (2023.02); H10N 52/01 (2023.02); H10N 52/101 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A structure, comprising:
a bottom electrode having linear sidewalls;
a storage element layer disposed on and in physical contact with the bottom electrode;
a top electrode disposed on and in physical contact with the storage element layer;
a selector disposed on and in physical contact with the top electrode, wherein the selector comprises a first conductive layer, a second conductive layer and a plurality of insulating layers disposed in between the first conductive layer and the second conductive layer; and
a metal hard mask layer disposed on the selector and the storage element layer, wherein the metal hard mask layer has slanted sidewalls, and the slanted sidewalls of the metal hard mask layer are aligned with slanted sidewalls of the selector, aligned with slanted sidewalls of the top electrode, and aligned with slanted sidewalls of the storage element layer; and
a dielectric layer covering the linear sidewalls of the bottom electrode;
a passivation layer covering the slanted sidewalls of the metal hard mask layer, the slanted sidewalls of the top electrode and the slanted sidewalls of the storage element layer, wherein the passivation layer is physically separated from the dielectric layer; and
an interconnection structure disposed on the metal hard mask layer, wherein the interconnection structure is electrically connected to a surface of the metal hard mask layer, and a maximum width of the interconnection structure is greater than a maximum width of the metal hard mask layer.