US 12,324,358 B2
Tall bottom electrode structure in embedded magnetoresistive random-access memory
Ashim Dutta, Clifton Park, NY (US); Lili Cheng, Rexford, NY (US); and Chih-Chao Yang, Glenmont, NY (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Dec. 1, 2021, as Appl. No. 17/539,316.
Prior Publication US 2023/0172073 A1, Jun. 1, 2023
Int. Cl. H10N 50/80 (2023.01); H10B 61/00 (2023.01); H10N 50/01 (2023.01)
CPC H10N 50/80 (2023.02) [H10B 61/00 (2023.02); H10N 50/01 (2023.02)] 12 Claims
OG exemplary drawing
 
1. A semiconductor structure comprising:
an embedded memory area interconnect structure and an embedded non-memory area interconnect structure, the memory area interconnect structure comprising metal interconnects formed in a substrate;
a first top contact on a metal interconnect of the non-memory area interconnect structure;
a bottom metal contact in a trench of dielectric material on a first metal interconnect of the memory area interconnect structure, a bottom surface of the bottom metal contact lower than a bottom surface of the first top contact;
a memory element stack pillar on the bottom metal contact;
a pillar encapsulation layer present on sidewalls of the memory element stack pillar, wherein:
the pillar encapsulation layer comprises a dielectric material; and
a bottom surface of the pillar encapsulation layer of the non-memory area interconnect structure is higher than a bottom surface of the pillar encapsulation layer of the memory area interconnect structure; and
a metal cap directly contacting a top surface of a second metal interconnect of the memory area interconnect structure, wherein:
the top surface of the metal cap is lower than a top surface of the bottom metal contact; and
the top surface of the metal cap directly contacts the bottom surface of the pillar encapsulation layer of the memory area interconnect structure.