US 12,324,311 B2
Display panel, pixel driving circuits, and display device
Hong Cheng, Wuhan (CN); Yanqing Guan, Wuhan (CN); Chao Tian, Wuhan (CN); Fei Ai, Wuhan (CN); and Guanghui Liu, Wuhan (CN)
Assigned to WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD., Wuhan (CN)
Appl. No. 17/771,484
Filed by WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD., Wuhan (CN)
PCT Filed Apr. 13, 2022, PCT No. PCT/CN2022/086573
§ 371(c)(1), (2) Date Apr. 24, 2022,
PCT Pub. No. WO2023/178748, PCT Pub. Date Sep. 28, 2023.
Claims priority of application No. 202210306179.8 (CN), filed on Mar. 25, 2022.
Prior Publication US 2023/0309342 A1, Sep. 28, 2023
Int. Cl. G09G 3/32 (2016.01); H10K 59/121 (2023.01); H10D 30/67 (2025.01); H10D 86/40 (2025.01); H10D 86/60 (2025.01)
CPC H10K 59/1213 (2023.02) [G09G 3/32 (2013.01); H10K 59/1216 (2023.02); G09G 2300/0426 (2013.01); G09G 2300/0842 (2013.01); G09G 2300/0861 (2013.01); G09G 2320/0233 (2013.01); G09G 2320/0242 (2013.01); H10D 30/6731 (2025.01); H10D 30/6745 (2025.01); H10D 30/6755 (2025.01); H10D 86/423 (2025.01); H10D 86/471 (2025.01); H10D 86/481 (2025.01); H10D 86/60 (2025.01)] 16 Claims
OG exemplary drawing
 
1. A display panel, comprising:
a plurality of light-emitting devices; and
a plurality of pixel driving circuits, wherein each of the pixel driving circuits is electrically connected to at least one of the light-emitting devices, each of the pixel driving circuits comprises driving transistors, the driving transistors and a corresponding light-emitting device are connected in series between a first voltage terminal and a second voltage terminal, and the driving transistors comprise a first transistor and a second transistor connected in parallel; and
wherein an absolute value of a threshold voltage of the first transistor is greater than an absolute value of a threshold voltage of the second transistor, and a carrier mobility of the first transistor is greater than a carrier mobility of the second transistor;
wherein the display panel further comprises:
a first semiconductor layer comprising an active layer of the first transistor;
a second semiconductor layer disposed on the first semiconductor layer and comprising an active layer of the second transistor;
a first metal layer disposed between the first semiconductor layer and the second semiconductor layer; and
a second metal layer disposed on a side of the second semiconductor layer away from the first metal layer;
wherein an orthographic projection of the active layer of the second transistor on the active layer of the first transistor overlaps the active layer of the first transistor;
wherein the first metal layer comprises a gate of the first transistor, the gate of the first transistor and the active layer of the first transistor at least partially overlap; the second metal layer comprises a gate of the second transistor, the gate of the second transistor and the active layer of the second transistor at least partially overlap, and an orthographic projection of the gate of the second transistor on the first metal layer overlaps the gate of the first transistor.