US 12,324,310 B2
Display device including a node connection line, a shielding portion and a driving voltage line
Junwon Choi, Yongin-si (KR); Yunkyeong In, Yongin-si (KR); Wonmi Hwang, Yongin-si (KR); and Junyong An, Yongin-si (KR)
Assigned to SAMSUNG DISPLAY CO., LTD., Gyeonggi-Do (KR)
Filed by SAMSUNG DISPLAY CO., LTD., Yongin-si (KR)
Filed on Dec. 8, 2023, as Appl. No. 18/534,370.
Application 18/534,370 is a continuation of application No. 17/680,563, filed on Feb. 25, 2022, granted, now 11,864,417.
Application 17/680,563 is a continuation of application No. 16/902,677, filed on Jun. 16, 2020, granted, now 11,264,432, issued on Mar. 1, 2022.
Application 16/902,677 is a continuation of application No. 16/135,476, filed on Sep. 19, 2018, granted, now 10,727,281, issued on Jul. 28, 2020.
Application 16/135,476 is a continuation of application No. 15/597,763, filed on May 17, 2017, granted, now 10,103,208, issued on Oct. 16, 2018.
Claims priority of application No. 10-2016-0074732 (KR), filed on Jun. 15, 2016.
Prior Publication US 2024/0107800 A1, Mar. 28, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/08 (2006.01); G09G 3/3233 (2016.01); G09G 3/3258 (2016.01); H10D 86/40 (2025.01); H10D 86/60 (2025.01); H10K 59/00 (2023.01); H10K 59/126 (2023.01); H10K 59/131 (2023.01)
CPC H10K 59/00 (2023.02) [G09G 3/3233 (2013.01); G09G 3/3258 (2013.01); H10D 86/481 (2025.01); H10D 86/60 (2025.01); G09G 2300/0426 (2013.01); G09G 2300/043 (2013.01); G09G 2300/0819 (2013.01); G09G 2300/0842 (2013.01); G09G 2300/0861 (2013.01); G09G 2310/0251 (2013.01); G09G 2310/0262 (2013.01); G09G 2320/043 (2013.01); H10K 59/126 (2023.02); H10K 59/131 (2023.02)] 19 Claims
OG exemplary drawing
 
1. A display device comprising:
a first transistor comprising a first semiconductor layer and a first gate electrode overlapping the first semiconductor layer;
a storage capacitor comprising an electrode overlapping the first gate electrode;
a first scan line extending in a first direction;
a second scan line extending in the first direction;
a data line extending in a second direction crossing the first direction;
a second transistor comprising a second semiconductor layer, wherein the first scan line comprises a second gate electrode of the second transistor, the second gate electrode overlaps the second semiconductor layer;
a third transistor comprising a third semiconductor layer, wherein the first scan line comprises two third gate electrodes of the third transistor, the third semiconductor layer comprises a first portion extending in the first direction and a second portion extending in the second direction, and the two third gate electrodes overlaps the first portion and the second portion of the third semiconductor layer, respectively;
a fourth transistor comprising a fourth semiconductor layer, wherein the second scan line comprises a fourth gate electrode overlapping the fourth semiconductor layer;
a driving voltage line extending in the second direction, wherein a portion of the driving voltage line overlaps a portion of the third semiconductor layer;
a node connection line positioned between the data line and the driving voltage line; and
a shielding portion, wherein an end portion of the shielding portion is disposed between the data line and the node connection line.