| CPC H10F 39/807 (2025.01) [H04N 25/70 (2023.01); H10F 39/8033 (2025.01); H10F 30/225 (2025.01)] | 34 Claims |
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1. A photoelectric conversion apparatus comprising:
a semiconductor layer having a first surface and a second surface, the second surface being a surface opposite to the first surface; and
a plurality of avalanche photodiodes arranged on the semiconductor layer and including a first avalanche photodiode, a second avalanche photodiode and a third avalanche photodiode,
wherein each of the plurality of avalanche photodiodes includes an avalanche multiplication unit formed by a first semiconductor region of a first conductivity type in which a carrier of a same conductivity type as a signal charge is regarded as a majority carrier and which is arranged at a first depth, and a second semiconductor region of a second conductivity type different from the first conductivity type and which is arranged at a second depth deeper than the first depth with respect to the first surface,
wherein a third semiconductor region of the second conductivity type is arranged between the first avalanche photodiode and the second avalanche photodiode,
wherein a fourth semiconductor region is arranged between the first avalanche photodiode and the second avalanche photodiode at a position shallower than the third semiconductor region with respect to the first surface,
wherein the fourth semiconductor region is a second conductivity type semiconductor region in which an impurity concentration of the second conductive type is lower than an impurity concentration of the second conductive type in the third semiconductor region, or a first conductivity type semiconductor region,
wherein the second semiconductor region is arranged in contact with the third semiconductor region,
wherein the first avalanche photodiode and the second avalanche photodiode are arranged adjacently in a first direction,
wherein the second avalanche photodiode and the third avalanche photodiode are arranged adjacently in a second direction orthogonal to the first direction,
wherein a distance between the first semiconductor region of the first avalanche photodiode and the first semiconductor region of the third avalanche photodiode is longer than a distance between the first semiconductor region of the first avalanche photodiode and the first semiconductor region of the second avalanche photodiode,
wherein an isolation region including a trench structure is arranged between the first avalanche photodiode and the second avalanche photodiode,
wherein the third semiconductor region and the fourth semiconductor region are arranged in a side wall portion of the trench structure,
wherein the first semiconductor region includes a top surface and a bottom surface, wherein the top surface of the first semiconductor region is arranged on the first surface of the semiconductor layer and the bottom surface is a surface opposite to the top surface of the first semiconductor region,
wherein the third semiconductor region includes a top surface and a bottom surface, wherein the bottom surface of the third semiconductor region is arranged on the second surface of the semiconductor layer and the top surface is a surface opposite to the bottom surface of the third semiconductor region, and
wherein the top surface of the third semiconductor region is deeper than the bottom surface of the first semiconductor region with respect to the first surface.
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