| CPC H10F 30/225 (2025.01) [H10F 71/00 (2025.01); H10F 77/148 (2025.01)] | 23 Claims |

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1. A method for manufacturing an integrated circuit including a single photon avalanche diode (SPAD), comprising:
implanting a first region doped with a first type of dopant in a semiconductor well doped with the first type of dopant;
implanting a second region doped with a second type of dopant opposite to the first type of dopant in the semiconductor well;
wherein the first and second regions form a PN junction of the SPAD;
wherein implanting the second region comprises implanting the second doped region at a surface of the semiconductor well and at a position that is centered in a photosensitive area of the SPAD; and
wherein implanting the first region comprises forming local variations in dopant concentration and further comprises:
a first implanting of a first volume at a position centered at a depth in contact with a bottom of the second region; and
a second implanting of a second volume laterally annularly surrounding the first volume and at a depth remote from the second doped region but joining the depth of the first volume, wherein the second implanting further comprises implanting a pattern inside the first volume.
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