| CPC H10D 89/10 (2025.01) [G06F 30/392 (2020.01)] | 20 Claims |
|
1. A semiconductor device comprising:
a plurality of standard cells in a first direction and a second direction, parallel to an upper surface of a substrate and intersecting with each other, and each of the plurality of standard cells having two or more gate structures and two or more active regions,
wherein the plurality of standard cells comprise first standard cells in a first standard cell region and a second standard cell region, defined in different positions in at least one of the first direction or the second direction, and the first standard cells provide a same circuit,
wherein the first standard cell in the first standard cell region comprises a first input line connecting input wirings that are connected to two or more gate structures of the first standard cell in the first standard cell region to each other, and a first output line connecting output wirings that are connected to two or more active regions of the first standard cell in the first standard cell region to each other, and
the first standard cell in the second standard cell region comprises a second input line connecting input wirings that are connected to two or more gate structures of the first standard cell in the second standard cell region to each other, and a second output line connecting output wirings that are connected to two or more active regions of the first standard cell in the second standard cell region to each other,
wherein a position of the first input line in the first standard cell region is different from a position of the second input line in the second standard cell region, or a position of the first output line in the first standard cell region is different from a position of the second output line in the second standard cell region.
|