| CPC H10D 84/85 (2025.01) [H10D 84/0179 (2025.01); H10D 84/0181 (2025.01); H10D 84/038 (2025.01)] | 15 Claims |
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1. A semiconductor device comprising:
a first active pattern and a second active pattern disposed on a substrate and being adjacent to each other;
a field insulating film disposed on the substrate, between the first active pattern and the second active pattern, and being in direct contact with the first active pattern and the second active pattern;
a first gate structure intersecting the first active pattern, on the substrate; and
a second gate structure intersecting the second active pattern, on the substrate,
wherein
the first gate structure includes a first gate insulating film, which is on the first active pattern, a first upper insertion film, which is on the first gate insulating film, and a first upper conductive film, which is on the first upper insertion film and in contact with the first upper insertion film,
the second gate structure includes a second gate insulating film, which is on the second active pattern, a second upper insertion film, which is on the second gate insulating film, and a second upper conductive film, which is on the second upper insertion film and in contact with the second upper insertion film,
each of the first upper insertion film and the second upper insertion film is an aluminum nitride film,
each of the first upper conductive film and the second upper conductive film includes aluminum,
the first upper insertion film is not in contact with the first gate insulating film,
the first upper conductive film is over the first upper insertion film, but not interposed between two adjacent separate portions of the first upper insertion film,
the second upper conductive film is over the second upper insertion film, and interposed between two adjacent separate portions of the second upper insertion film,
the second upper insertion film is in direct contact with the second gate insulating film,
the first gate structure further includes a lower insertion film and a lower conductive film, with the aluminum nitride film of the first upper insertion film disposed between the lower insertion film and the first upper conductive film and spaced apart from the lower insertion film on the first active pattern, the lower conductive film directly contacting the first upper insertion film and the lower insertion film, and the lower insertion film including a nitride or an oxide of a metal having an electronegativity of about 1.5 or higher,
the first active pattern is disposed in a p-type metal-oxide semiconductor (PMOS) region, and
the second active pattern is disposed in an n-type metal-oxide semiconductor (NMOS) region.
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