| CPC H10D 84/834 (2025.01) [H01L 21/3212 (2013.01); H10D 30/0241 (2025.01); H10D 30/6211 (2025.01); H10D 84/0158 (2025.01); H10D 84/038 (2025.01)] | 20 Claims |
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1. A method comprising:
receiving a semiconductor structure including:
a semiconductor substrate;
a fin structure over the semiconductor substrate;
a liner layer on a sidewall of the fin structure; and
a first dielectric layer over the semiconductor substrate and on a side surface of the liner layer;
recessing the first dielectric layer and the liner layer to form a recessed first dielectric layer, a recessed liner layer, and to expose a first portion of the fin structure;
trimming the exposed first portion of the fin structure to form a trimmed fin structure;
depositing a second dielectric layer over the first dielectric layer and over the trimmed fin structure, the second dielectric layer having a top surface extending over a top surface of the trimmed fin structure;
recessing the second dielectric layer to expose a second portion of the trimmed fin structure, the recessed second dielectric layer having a top surface extending over a top surface of the recessed liner layer and below a top surface of the trimmed fin structure; and
forming a gate structure over the recessed second dielectric layer and the trimmed fin structure, such that the gate structure engages with a channel portion of the fin structure.
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