US 12,324,228 B2
Methods of resistance and capacitance reduction to circuit output nodes
Po-Chia Lai, Fremont, CA (US); Shang-Wei Fang, Hsinchu (TW); Meng-Hung Shen, Hsinchu County (TW); Jiann-Tyng Tzeng, Hsinchu (TW); Ting-Wei Chiang, New Taipei (TW); Jung-Chan Yang, Taoyuan (TW); and Stefan Rusu, Sunnyvale, CA (US)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed on Apr. 13, 2022, as Appl. No. 17/720,184.
Application 17/720,184 is a continuation of application No. 16/787,964, filed on Feb. 11, 2020, granted, now 11,309,311.
Prior Publication US 2022/0238515 A1, Jul. 28, 2022
Int. Cl. H10D 84/80 (2025.01); G06F 30/392 (2020.01); G06F 30/394 (2020.01); H01L 23/485 (2006.01); H01L 23/64 (2006.01); H10D 89/10 (2025.01)
CPC H10D 84/811 (2025.01) [G06F 30/392 (2020.01); G06F 30/394 (2020.01); H01L 23/485 (2013.01); H01L 23/642 (2013.01); H01L 23/647 (2013.01); H10D 89/10 (2025.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit, comprising:
a first conductive pattern that is disposed in a first layer and configured as a terminal of an inverter;
at least one first conductive segment that is disposed in a second layer above the first layer and configured to transmit an output signal output from the inverter;
a first via contacting the first conductive pattern and the at least one first conductive segment to transmit the output signal, wherein an area, contacting the first conductive pattern, of the first via is smaller than an area, contacting the at least one first conductive segment, of the first via; and
a gate that is disposed in the first layer and adjacent to the first conductive pattern, wherein the gate and the first conductive pattern extend in a same direction.