US 12,324,219 B2
Integrated circuit including dipole incorporation for threshold voltage tuning in transistors
Lung-Kun Chu, Hsinchu (TW); Mao-Lin Huang, Hsinchu (TW); Chung-Wei Hsu, Hsinchu (TW); Jia-Ni Yu, Hsinchu (TW); Kuo-Cheng Chiang, Hsinchu (TW); Kuan-Lun Cheng, Hsinchu (TW); and Chih-Hao Wang, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jan. 5, 2024, as Appl. No. 18/406,025.
Application 18/406,025 is a continuation of application No. 17/370,843, filed on Jul. 8, 2021, granted, now 11,894,367.
Prior Publication US 2024/0145470 A1, May 2, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H10D 84/01 (2025.01); H10D 30/67 (2025.01); H10D 84/03 (2025.01)
CPC H10D 84/0128 (2025.01) [H10D 30/6735 (2025.01); H10D 84/0144 (2025.01); H10D 84/038 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
forming a first semiconductor fin corresponding to a channel region of a first FinFET transistor;
depositing a first interfacial dielectric layer on the first semiconductor fin;
depositing a dipole-inducing layer on the first interfacial dielectric layer;
depositing a first high-K dielectric layer on the dipole-inducing layer after depositing the dipole-inducing layer such that the dipole inducing layer is positioned between the first interfacial dielectric layer and the first high-K dielectric layer; and
forming a dipole layer from the dipole-inducing layer and at least one of high-K dielectric layer and the interfacial dielectric layer on the first semiconductor fin by performing a thermal anneal process.