US 12,324,213 B2
Stress layout optimization for device performance
Dirk Utess, Dresden (DE); Zhixing Zhao, Dresden (DE); Dominik M. Kleimaier, Dresden (DE); Irfan A. Saadat, Santa Clara, CA (US); and Florent Ravaux, Wimille (FR)
Assigned to GLOBALFOUNDRIES U.S. Inc., Malta, NY (US)
Filed by GLOBALFOUNDRIES U.S. Inc., Malta, NY (US)
Filed on Mar. 28, 2023, as Appl. No. 18/127,206.
Application 18/127,206 is a division of application No. 16/556,796, filed on Aug. 30, 2019, granted, now 11,664,432.
Prior Publication US 2023/0238439 A1, Jul. 27, 2023
Int. Cl. H01L 29/417 (2006.01); H01L 27/092 (2006.01); H10D 30/69 (2025.01); H10D 64/01 (2025.01); H10D 64/23 (2025.01); H10D 84/85 (2025.01)
CPC H10D 64/258 (2025.01) [H10D 30/794 (2025.01); H10D 64/01 (2025.01); H10D 84/85 (2025.01)] 13 Claims
OG exemplary drawing
 
1. A structure comprising:
at least a first gate structure;
at least a second gate structure;
at least a first contact positioned at a first distance away from the first gate structure; and
at least a second contact positioned at a second distance away from the second gate structure, wherein
the first contact with the first distance provides a first stress component to a channel region of the first device, and
the second contact with the second distance provides a second stress component to a channel region of the second device,
the first gate structure is a PFET device, the second gate structure is an NFET device, and the first contact is closer to the PFET device than the second contact is from the NFET device.