US 12,324,210 B2
Bipolar junction transistor with gate over terminals
Ming-Shuan Li, Zhudong Township (TW); Zi-Ang Su, Longtan Township (TW); and Ying-Keung Leung, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jun. 21, 2024, as Appl. No. 18/750,063.
Application 17/589,180 is a division of application No. 16/785,124, filed on Feb. 7, 2020, granted, now 11,239,330, issued on Feb. 1, 2022.
Application 18/750,063 is a continuation of application No. 18/366,834, filed on Aug. 8, 2023, granted, now 12,051,729.
Application 18/366,834 is a continuation of application No. 17/589,180, filed on Jan. 31, 2022, granted, now 11,843,038, issued on Dec. 12, 2023.
Prior Publication US 2024/0339508 A1, Oct. 10, 2024
Int. Cl. H10D 64/23 (2025.01); H10D 10/00 (2025.01); H10D 10/01 (2025.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 64/27 (2025.01)
CPC H10D 64/231 (2025.01) [H10D 10/00 (2025.01); H10D 10/01 (2025.01); H10D 30/0243 (2025.01); H10D 30/62 (2025.01); H10D 64/281 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A bipolar junction transistor (BJT) comprising:
an emitter comprising first epitaxy regions and a first gate structure between adjacent ones of the first epitaxy regions;
a base comprising second epitaxy regions and a second gate structure between adjacent ones of the second epitaxy regions; and
a collector comprising third epitaxy regions and a third gate structure between adjacent ones of the third epitaxy regions, wherein the first gate structure, the second gate structure, and the third gate structure are physically separated, and wherein the base is disposed between the emitter and the collector.