US 12,324,207 B2
Channel protection of gate-all-around devices for performance optimization
Maruf Amin Bhuiyan, Albany, NY (US); Julien Frougier, Albany, NY (US); Ruilong Xie, Niskayuna, NY (US); and Eric Miller, Watervliet, NY (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Dec. 3, 2021, as Appl. No. 17/457,634.
Prior Publication US 2023/0178618 A1, Jun. 8, 2023
Int. Cl. H10D 64/01 (2025.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01)
CPC H10D 64/018 (2025.01) [H10D 30/024 (2025.01); H10D 30/6713 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/115 (2025.01); H10D 62/121 (2025.01); H10D 64/021 (2025.01); H10D 84/0128 (2025.01); H10D 84/013 (2025.01); H10D 84/0147 (2025.01); H10D 84/0151 (2025.01); H10D 84/0158 (2025.01); H10D 84/038 (2025.01)] 20 Claims
OG exemplary drawing
 
10. A method of forming a semiconductor structure, comprising:
forming a plurality of channel layers vertically stacked over a substrate;
forming an inner spacer between each of the plurality of channel layers;
forming source/drain regions in contact with opposite ends of a first portion of the plurality of channel layers; and
forming a first dielectric layer on opposite ends of a second portion of the plurality of channel layers located on a spacer region that is adjacent to the source/drain regions, a width of the first dielectric layer and the second portion of the plurality of channel layers being equal to a width of the inner spacer located between each of the plurality of channel layers.