US 12,324,206 B2
Semiconductor devices and methods of manufacturing thereof
Mark I. Gardner, Albany, NY (US); H. Jim Fulford, Albany, NY (US); and Partha Mukhopadhyay, Albany, NY (US)
Assigned to Tokyo Electron Limited, Tokyo (JP)
Filed by Tokyo Electron Limited, Tokyo (JP)
Filed on Oct. 27, 2022, as Appl. No. 17/975,352.
Prior Publication US 2024/0145576 A1, May 2, 2024
Int. Cl. H10D 64/01 (2025.01); H10D 30/01 (2025.01); H10D 30/43 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 62/13 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01)
CPC H10D 64/017 (2025.01) [H10D 30/014 (2025.01); H10D 30/43 (2025.01); H10D 30/6735 (2025.01); H10D 30/6741 (2025.01); H10D 30/6743 (2025.01); H10D 30/6757 (2025.01); H10D 62/121 (2025.01); H10D 62/151 (2025.01); H10D 64/01 (2025.01); H10D 64/015 (2025.01); H10D 64/018 (2025.01); H10D 64/021 (2025.01); H10D 84/0167 (2025.01); H10D 84/017 (2025.01); H10D 84/0184 (2025.01); H10D 84/038 (2025.01); H10D 84/85 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
forming a fin structure over a substrate, the fin structure including alternating first semiconductor layers and second semiconductor layers stacked along a vertical direction, the first and the second semiconductor layers having different composition;
forming a dummy gate structure over the fin structure;
depositing an outer spacer layer on the dummy gate structure;
performing a plasma doping process to form source/drain regions in each second semiconductor layer adjacent the dummy gate structure along a lateral direction, wherein a portion of each second semiconductor layer interposing between the source/drain regions defines a channel region;
forming a dielectric layer over the fin structure;
removing the dummy gate structure to form a gate trench in the dielectric layer;
selectively removing the first semiconductor layers to form openings interleaved with the second semiconductor layers; and
forming a metal gate structure in the gate trench and the openings.