US 12,324,198 B2
Semiconductor device and manufacture method thereof
Teng Huang, Wuhan (CN); Ziqun Hua, Wuhan (CN); Yanwei Shi, Wuhan (CN); and Lan Yao, Wuhan (CN)
Assigned to YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed by YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed on Mar. 23, 2022, as Appl. No. 17/702,008.
Application 17/702,008 is a continuation of application No. PCT/CN2021/115748, filed on Aug. 31, 2021.
Prior Publication US 2023/0064099 A1, Mar. 2, 2023
Int. Cl. H01L 29/06 (2006.01); H01L 21/762 (2006.01); H10D 62/10 (2025.01)
CPC H10D 62/115 (2025.01) [H01L 21/76224 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a first shallow trench isolation trench corresponding to a first transistor and a second shallow trench isolation trench corresponding to a second transistor; and
a first bottom isolation layer into the first shallow trench isolation trench and a second bottom isolation layer into the second shallow trench isolation trench, a thickness of the second bottom isolation layer being less than a thickness of the first bottom isolation layer,
wherein:
a first gate structure, corresponding to the first transistor, extends onto the first bottom isolation layer to have a first junction depth, and a second gate structure, corresponding to the second transistor, extends onto the second bottom isolation layer to have a second junction depth, the first junction depth being different from the second junction depth; and
the first bottom isolation layer and the second bottom isolation layer, in a location between the first gate structure and the second gate structure, are discontinuous.