US 12,324,194 B2
Source/drain engineering for ferroelectric field effect transistors
Chih-Yu Chang, New Taipei (TW); Chun-Chieh Lu, Taipei (TW); Yu-Chien Chiu, Hsinchu County (TW); Ya-Yun Cheng, Taichung (TW); Yu-Ming Lin, Hsinchu (TW); Sai-Hooi Yeong, Hsinchu County (TW); and Hung-Wei Li, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed on May 19, 2022, as Appl. No. 17/748,076.
Prior Publication US 2023/0378350 A1, Nov. 23, 2023
Int. Cl. H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01); H10D 30/67 (2025.01); H10D 30/69 (2025.01); H10D 64/68 (2025.01); H10D 99/00 (2025.01)
CPC H10D 30/701 (2025.01) [H10D 30/6713 (2025.01); H10D 30/6755 (2025.01); H10D 30/6757 (2025.01); H10D 64/689 (2025.01); H10D 99/00 (2025.01)] 21 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a gate;
a ferroelectric layer disposed on the gate;
a first channel layer disposed on the ferroelectric layer;
a second channel layer disposed on the ferroelectric layer; and
source and drain regions disposed on the first channel layer;
wherein the first channel layer includes a first thickness and the second channel layer includes a second thickness, and a ratio of the first thickness and the second thickness is less than ⅗ and greater than 1/10.