	US 12,324,191 B2
	Transistor gate structures and methods of forming the same
Shih-Yao Lin, New Taipei (TW); Chen-Ping Chen, Toucheng Township (TW); Hsiaowen Lee, Hsinchu (TW); and Chih-Han Lin, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Aug. 2, 2023, as Appl. No. 18/363,968.
Application 18/363,968 is a division of application No. 17/336,599, filed on Jun. 2, 2021, granted, now 12,142,655.
Claims priority of provisional application 63/059,710, filed on Jul. 31, 2020.
Prior Publication US 2023/0411483 A1, Dec. 21, 2023
Int. Cl. H10D 30/67 (2025.01); H01L 21/02 (2006.01); H01L 21/285 (2006.01); H10D 30/01 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 64/62 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01)

CPC H10D 30/6735 (2025.01) [H01L 21/02532 (2013.01); H01L 21/0259 (2013.01); H01L 21/28518 (2013.01); H10D 30/031 (2025.01); H10D 30/6713 (2025.01); H10D 30/6757 (2025.01); H10D 62/118 (2025.01); H10D 64/017 (2025.01); H10D 64/018 (2025.01); H10D 64/62 (2025.01); H10D 84/0167 (2025.01); H10D 84/017 (2025.01); H10D 84/0184 (2025.01); H10D 84/0186 (2025.01); H10D 84/0188 (2025.01); H10D 84/038 (2025.01); H10D 84/85 (2025.01)]

19 Claims

1. A device comprising:

an isolation region;

nanostructures protruding above a top surface of the isolation region;

a gate structure wrapped around the nanostructures, the gate structure having a bottom surface contacting the isolation region, the bottom surface of the gate structure extending away from a sidewall of the nanostructures a first distance in a direction that is parallel to the top surface of the isolation region, the gate structure having a sidewall disposed a second distance from the sidewall of the nanostructures in the direction that is parallel to the top surface of the isolation region, the first distance less than the second distance; and

a hybrid fin on the sidewall of the gate structure.