US 12,324,189 B2
Semiconductor device and manufacturing method thereof
Shunpei Yamazaki, Tokyo (JP); Kengo Akimoto, Atsugi (JP); and Daisuke Kawae, Chiba (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by SEMICONDUCTOR ENERGY LABORATORY CO., LTD., Atsugi (JP)
Filed on Jan. 24, 2022, as Appl. No. 17/582,038.
Application 17/582,038 is a continuation of application No. 16/846,569, filed on Apr. 13, 2020, granted, now 11,239,332.
Application 16/846,569 is a continuation of application No. 16/180,580, filed on Nov. 5, 2018, granted, now 10,665,684, issued on May 26, 2020.
Application 16/180,580 is a continuation of application No. 15/841,891, filed on Dec. 14, 2017, granted, now 10,411,102, issued on Sep. 10, 2019.
Application 15/841,891 is a continuation of application No. 15/074,287, filed on Mar. 18, 2016, granted, now 9,847,396, issued on Dec. 19, 2017.
Application 15/074,287 is a continuation of application No. 14/451,680, filed on Aug. 5, 2014, granted, now 9,293,545, issued on Mar. 22, 2016.
Application 14/451,680 is a continuation of application No. 13/763,874, filed on Feb. 11, 2013, granted, now 8,803,146, issued on Aug. 12, 2014.
Application 13/763,874 is a continuation of application No. 12/613,769, filed on Nov. 6, 2009, granted, now 8,373,164, issued on Feb. 12, 2013.
Application 12/613,769 is a continuation of application No. 12/606,262, filed on Oct. 27, 2009, abandoned.
Claims priority of application No. 2008-287187 (JP), filed on Nov. 7, 2008.
Prior Publication US 2022/0149164 A1, May 12, 2022
Int. Cl. H10D 30/67 (2025.01); H01L 21/02 (2006.01); H10D 86/01 (2025.01); H10D 86/40 (2025.01); H10D 86/60 (2025.01); H10K 10/46 (2023.01); H10K 10/84 (2023.01)
CPC H10D 30/6729 (2025.01) [H10D 30/67 (2025.01); H10D 30/6713 (2025.01); H10D 30/6739 (2025.01); H10D 30/6755 (2025.01); H10D 30/6757 (2025.01); H10D 86/0231 (2025.01); H10D 86/423 (2025.01); H10D 86/60 (2025.01); H10K 10/46 (2023.02); H10K 10/462 (2023.02); H10K 10/466 (2023.02); H10K 10/84 (2023.02); H01L 21/02554 (2013.01); H01L 21/02565 (2013.01); H01L 21/02631 (2013.01)] 3 Claims
OG exemplary drawing
 
1. A display device comprising:
a first driver circuit over a substrate, the first driver circuit comprising a first transistor and a second transistor;
a second driver circuit over the substrate; and
a pixel portion over the substrate, the pixel portion comprising a third transistor, a fourth transistor, and a light-emitting element,
wherein the first driver circuit comprises:
a first gate electrode and a second gate electrode over the substrate;
a first wiring over the first gate electrode, the first wiring functioning as one of a source electrode and a drain electrode of the first transistor;
a second wiring over the first gate electrode and the second gate electrode, the second wiring functioning as the other of the source electrode and the drain electrode of the first transistor and one of a source electrode and a drain electrode of the second transistor;
a third wiring over the second gate electrode, the third wiring functioning as the other of the source electrode and the drain electrode of the second transistor;
a first oxide semiconductor layer over the first wiring and the second wiring, the first oxide semiconductor layer in contact with a side surface and a top surface of the first wiring and a first side surface and a first top surface of the second wiring; and
a second oxide semiconductor layer over the second wiring and the third wiring, the second oxide semiconductor layer in contact with a second side surface and a second top surface of the second wiring and a side surface and a top surface of the third wiring,
wherein the first oxide semiconductor layer is not in contact with the second oxide semiconductor layer,
wherein the third transistor comprises:
a source electrode layer and a drain electrode layer over the substrate; and
a third oxide semiconductor layer over the source electrode layer and the drain electrode layer, the third oxide semiconductor layer in contact with a side surface of each of the source electrode layer and the drain electrode layer,
wherein a gate electrode of the third transistor is electrically connected to the first driver circuit,
wherein a gate electrode of the fourth transistor is electrically connected to the second driver circuit, and
wherein the fourth transistor is positioned between a driving transistor and the light-emitting element.