US 12,324,185 B2
Semiconductor device, FinFET device and methods of forming the same
Po-Hsien Cheng, Hsinchu (TW); Jr-Hung Li, Hsinchu County (TW); Tai-Chun Huang, Hsin-Chu (TW); Tze-Liang Lee, Hsinchu (TW); Chung-Ting Ko, Kaohsiung (TW); Jr-Yu Chen, Taipei (TW); and Wan-Chen Hsieh, Hsinchu (TW)
Assigned to Taiwan Semicoductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Apr. 15, 2024, as Appl. No. 18/636,217.
Application 18/636,217 is a division of application No. 17/685,401, filed on Mar. 3, 2022, granted, now 11,984,485.
Application 17/685,401 is a continuation of application No. 16/805,862, filed on Mar. 2, 2020, granted, now 11,271,083, issued on Mar. 8, 2022.
Claims priority of provisional application 62/906,745, filed on Sep. 27, 2019.
Prior Publication US 2024/0258390 A1, Aug. 1, 2024
Int. Cl. H10D 30/62 (2025.01); H10D 30/01 (2025.01); H10D 62/13 (2025.01); H10D 64/01 (2025.01)
CPC H10D 30/6219 (2025.01) [H10D 30/024 (2025.01); H10D 30/6211 (2025.01); H10D 62/151 (2025.01); H10D 64/017 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A method of forming a semiconductor device, comprising:
providing a substrate having a fin and an isolation structure aside the fin;
forming a gate structure across the fin;
forming a S/D region in and/or on the fin and aside the gate structure;
forming an interlayer dielectric layer on the substrate to cover the gate structure and the S/D region;
removing a portion of the interlayer dielectric layer to form an opening exposing the S/D region and the isolation structure adjacent to the S/D region;
forming a dummy contact to cover the S/D region exposed by the opening;
forming a protection layer to cover sidewalls of the dummy contact;
forming an additional dielectric layer to fill the opening and laterally aside the dummy contact;
removing the dummy contact; and
removing a portion of the protection layer previously covering the sidewalls of the dummy contact.