| CPC H10D 30/6219 (2025.01) [H10B 10/12 (2023.02); H10D 30/0215 (2025.01); H10D 64/017 (2025.01); H10D 64/258 (2025.01); H10D 84/0153 (2025.01); H10D 84/0186 (2025.01); H10D 84/0193 (2025.01); H10D 84/853 (2025.01); H10D 64/667 (2025.01)] | 8 Claims |
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1. A memory device comprising:
a semiconductor fin;
a metal gate stack comprising a gate dielectric layer, a work function layer disposed over the gate dielectric layer, and a conductive metal deposited over the gate dielectric layer and the work function layer, the metal gate stack formed over and in direct contact with a channel region of the semiconductor fin; and
a cross-couple contact arranged on the metal gate stack, the cross-couple contact comprising a metal, a first sidewall, a second sidewall, and a bottom endwall;
wherein the bottom endwall is entirely above the semiconductor fin, and the first sidewall and the second sidewall extend above two opposing sides of the bottom endwall;
wherein the work function layer of the metal gate stack is in direct contact with each of the first sidewall and the bottom endwall of the cross-couple contact;
wherein the gate dielectric layer is in direct contact with the second sidewall of the cross-couple contact, is not in direct contact with the first sidewall, and is not in direct contact with the bottom endwall of the cross-couple contact; and
wherein the work function layer is positioned directly between the cross-coupled contact and the semiconductor fin, thereby physically separating the cross-coupled contact from the semiconductor fin.
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