US 12,324,182 B2
Connector via structures for nanostructures and methods of forming the same
Li-Zhen Yu, New Taipei (TW); Chia-Hao Chang, Hsinchu (TW); Lin-Yu Huang, Hsinchu (TW); Cheng-Chi Chuang, New Taipei (TW); and Chih-Hao Wang, Baoshan Township (TW)
Assigned to Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed on May 5, 2023, as Appl. No. 18/312,666.
Application 18/312,666 is a continuation of application No. 16/910,125, filed on Jun. 24, 2020, granted, now 11,682,730.
Prior Publication US 2023/0275154 A1, Aug. 31, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H10D 30/62 (2025.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H10D 30/01 (2025.01); H10D 64/27 (2025.01); H10D 64/66 (2025.01)
CPC H10D 30/62 (2025.01) [H01L 23/5226 (2013.01); H01L 23/528 (2013.01); H10D 30/024 (2025.01); H10D 30/6219 (2025.01); H10D 64/517 (2025.01); H10D 64/668 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A device structure comprising:
a semiconductor nanostructure located on a front surface of an backside insulating matrix layer and comprising a field effect transistor that includes a first active region and a second active region that comprise a source region and a drain region;
an epitaxial semiconductor material portion laterally spaced from the semiconductor nanostructure;
a backside metal interconnect structure located on a bottom surface of the backside insulating matrix layer; and
an electrically conductive path connecting the first active region and the backside metal interconnect structure and comprising a connector via structure in contact with a sidewall of the epitaxial semiconductor material portion.