US 12,324,180 B2
Integrated design for III-Nitride devices
Yifeng Wu, Goleta, CA (US); and John Kirk Gritters, Santa Barbara, CA (US)
Assigned to Transphorm Technology, Inc., Goleta, CA (US)
Filed by Transphorm Technology, Inc., Goleta, CA (US)
Filed on Sep. 20, 2023, as Appl. No. 18/471,263.
Application 18/471,263 is a continuation of application No. 17/047,602, granted, now 11,810,971, previously published as PCT/US2020/024015, filed on Mar. 20, 2020.
Claims priority of provisional application 62/821,946, filed on Mar. 21, 2019.
Prior Publication US 2024/0014312 A1, Jan. 11, 2024
Int. Cl. H01L 29/778 (2006.01); H01L 23/48 (2006.01); H10D 30/47 (2025.01); H10D 62/85 (2025.01)
CPC H10D 30/475 (2025.01) [H01L 23/481 (2013.01); H10D 62/8503 (2025.01)] 14 Claims
OG exemplary drawing
 
1. An electronic component, comprising:
an enhancement-mode transistor;
a depletion-mode transistor comprising a conductive substrate; and
a package comprising a conductive structural package base, the package enclosing both the enhancement-mode transistor and the depletion-mode transistor; wherein
a drain electrode of the depletion-mode transistor is electrically connected to a drain lead of the package, a gate electrode of the enhancement-mode transistor is electrically connected to a gate lead of the package, a source electrode of the enhancement-mode transistor is electrically connected to the conductive structural package base; wherein
a gate electrode of the depletion-mode transistor is electrically connected to the conductive substrate by a conductive via, wherein the conductive substrate is directly contacting and electrically connected to the conductive structural package base, and the conductive structural package base is electrically connected to a source lead of the package.