US 12,324,177 B2
Semiconductor device and method for manufacturing the same
Hirofumi Kida, Toyota (JP); Hidemoto Tomita, Toyota (JP); Tomohiko Mori, Nagakute (JP); and Hideya Yamadera, Nagakute (JP)
Assigned to DENSO CORPORATION, Kariya (JP)
Filed by DENSO CORPORATION, Kariya (JP)
Filed on Apr. 18, 2022, as Appl. No. 17/722,519.
Application 17/722,519 is a continuation of application No. PCT/JP2019/041752, filed on Oct. 24, 2019.
Prior Publication US 2022/0238703 A1, Jul. 28, 2022
Int. Cl. H10D 30/83 (2025.01); H10D 30/01 (2025.01); H10D 62/85 (2025.01)
CPC H10D 30/051 (2025.01) [H10D 30/83 (2025.01); H10D 62/8503 (2025.01)] 3 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a nitride semiconductor layer sectioned into an element part and a peripheral withstand voltage part on a periphery of the element part, the nitride semiconductor layer having a first main surface and a second main surface opposite to the first main surface;
a source electrode disposed on the first main surface of the nitride semiconductor layer;
a drain electrode disposed on the second main surface of the nitride semiconductor layer; and
an insulating gate portion,
wherein the nitride semiconductor layer includes:
a first conductivity type drift region provided in the element part and the peripheral withstand voltage part;
a first conductivity type JFET region provided in the element part, the JFET region arranged on the drift region and embedded in a first groove provided on the first main surface of the nitride semiconductor layer;
a second conductivity type body region provided in the element part, the body region arranged on the drift region and adjacent to the JFET region; and
a first conductivity type source region provided in the element part, the source region separated from the JFET region by the body region,
wherein the insulating gate portion is provided in the element part and disposed to face a channel portion of the body region that separates the JFET region and the source region,
wherein the nitride semiconductor layer is formed with a second groove on the first main surface in the peripheral withstand voltage part,
wherein an inclination angle of a side surface of the first groove adjacent to the channel portion is smaller than an inclination angle of a side surface of the second groove,
wherein the side surface of the first groove adjacent to the channel portion has a contour exposed on the first main surface of the nitride semiconductor layer, and the contour of the side surface of the first groove is parallel to a m-plane, and
wherein the side surface of the second groove has a contour exposed on the first main surface of the nitride semiconductor layer, and the contour of the side surface of the second groove is parallel to an a-plane.