US 12,324,161 B2
Annealed seed layer to improve ferroelectric properties of memory layer
Song-Fu Liao, Taipei (TW); Rainer Yen-Chieh Huang, Changhua County (TW); Hai-Ching Chen, Hsinchu (TW); and Chung-Te Lin, Tainan (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jan. 23, 2024, as Appl. No. 18/419,987.
Application 17/882,012 is a division of application No. 17/184,892, filed on Feb. 25, 2021, granted, now 11,690,228, issued on Jun. 27, 2023.
Application 18/419,987 is a continuation of application No. 17/882,012, filed on Aug. 5, 2022, granted, now 11,917,831.
Prior Publication US 2024/0164111 A1, May 16, 2024
Int. Cl. H01L 21/02 (2006.01); H01L 21/768 (2006.01); H10B 51/30 (2023.01); H10B 53/30 (2023.01)
CPC H10B 51/30 (2023.02) [H01L 21/76876 (2013.01); H10B 53/30 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
forming a seed layer over a substrate;
annealing the seed layer to form an annealed seed layer;
forming a memory layer over the annealed seed layer, wherein the memory layer is epitaxially grown from the anneal seed layer; and
forming a conductive structure over the memory layer;
wherein a thickness of the seed layer before the annealing is the same as a thickness of the annealed seed layer upon completion of the annealing.
 
8. A method, comprising:
forming a seed layer overlying a substrate;
annealing the seed layer, wherein an orthorhombic crystalline phase increases in the seed layer from a beginning of the annealing to an end of the annealing;
forming a ferroelectric layer overlying and directly on the seed layer; and
forming a conductive structure overlying the ferroelectric layer;
wherein the forming of the seed layer and the annealing are performed within a common process chamber, wherein the forming of the seed layer comprises: adding a precursor vapor formed from an inert gas and a metal to the common process chamber; and adding an oxygen gas to the common process chamber after the adding the precursor vapor, and wherein the annealing is performed after the forming of the seed layer.
 
14. A method, comprising:
forming a conductive wire over a substrate;
forming a memory cell atop the conductive wire and comprising:
a ferroelectric seed layer;
a semiconductor layer overlying the ferroelectric seed layer; and
a ferroelectric memory layer between the ferroelectric seed layer and the semiconductor layer, and directly contacting the ferroelectric seed layer; and
forming an etch stop layer;
wherein the etch stop layer is on sidewalls of the ferroelectric seed layer, and further has a top surface and a bottom surface respectively recessed relative to a top surface of the ferroelectric memory layer and elevated relative to a top surface of the conductive wire, after the forming of the memory cell and the forming of the etch stop layer.