US 12,324,159 B2
Vertical thin-film transistor and application as bit-line connector for 3-dimensional memory arrays
Tianhong Yan, Saratoga, CA (US); Scott Brad Herner, Portland, OR (US); Jie Zhou, San Jose, CA (US); Wu-Yi Henry Chien, San Jose, CA (US); and Eli Harari, Saratoga, CA (US)
Assigned to SUNRISE MEMORY CORPORATION, San Jose, CA (US)
Filed by SunRise Memory Corporation, San Jose, CA (US)
Filed on Feb. 8, 2024, as Appl. No. 18/436,365.
Application 18/436,365 is a continuation of application No. 17/804,986, filed on Jun. 1, 2022, granted, now 11,910,612.
Application 17/804,986 is a continuation of application No. 16/786,463, filed on Feb. 10, 2020, granted, now 11,398,492, issued on Jul. 26, 2022.
Claims priority of provisional application 62/947,405, filed on Dec. 12, 2019.
Claims priority of provisional application 62/804,080, filed on Feb. 11, 2019.
Prior Publication US 2024/0179919 A1, May 30, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H10B 43/40 (2023.01); H01L 21/02 (2006.01); H01L 21/225 (2006.01); H01L 21/311 (2006.01); H01L 21/3205 (2006.01); H01L 23/528 (2006.01); H01L 29/45 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01)
CPC H10B 43/40 (2023.02) [H01L 21/02164 (2013.01); H01L 21/0217 (2013.01); H01L 21/02532 (2013.01); H01L 21/02592 (2013.01); H01L 21/2251 (2013.01); H01L 21/31111 (2013.01); H01L 21/32053 (2013.01); H01L 23/528 (2013.01); H01L 29/458 (2013.01); H01L 29/665 (2013.01); H01L 29/66742 (2013.01); H01L 29/78642 (2013.01); H10B 43/10 (2023.02); H10B 43/27 (2023.02)] 16 Claims
OG exemplary drawing
 
1. A memory circuit formed on a semiconductor substrate having a planar surface, the semiconductor substrate having formed therein circuitry for memory operations, the memory circuit comprising:
an array of memory strings, wherein each memory string comprises a plurality of memory transistors and a common source or drain region coupled to each memory transistor of the memory string;
an interconnect layer formed above and parallel the planar surface of the semiconductor substrate, the interconnect layer having a plurality of conductors each being electrically connected to a portion of the circuitry for memory operations; and
one or more select transistors each formed above, alongside or below the array of memory strings, but above the planar surface of the semiconductor substrate, wherein each select transistor (i) is electrically connected between one of the conductors in the interconnect layer and the common source or drain region of a corresponding memory string, (ii) comprises a channel region, a drain region, a source region and a gate electrode, wherein the drain region, the source region and the gate electrode are each formed out of a conductive material, and (iii) electrically connects, when rendered conducting, one of the conductors in the interconnect layer to the common source or drain region of a corresponding memory string.