| CPC H10B 43/27 (2023.02) [H10B 43/35 (2023.02)] | 6 Claims |

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1. A semiconductor memory device comprising:
a stacked body including a plurality of insulating films and a plurality of first electrode films alternately stacked in a first direction;
an insulating member extending through the stacked body in the first direction and extending in the stacked body in a second direction crossing the first direction, and separating the stacked body in a third direction crossing the first direction and the second direction;
a first pillar including a semiconductor, and extending through the stacked body in the first direction;
a bit line extending in the third direction below the stacked body and electrically connected to a lower end of the first pillar; and
a source line extending in the third direction above the bit line and electrically connected to an upper end of the first pillar, wherein the insulating member includes a lower portion, an upper portion, and a middle portion between the lower portion and the upper portion,
the lower portion has a first width in the third direction,
the upper portion has a second width in the third direction,
the middle portion has a third width in the third direction,
the third width is greater than the first width and the second width, and
the first width is greater than the second width.
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