| CPC H10B 41/60 (2023.02) [H10B 41/27 (2023.02)] | 20 Claims |
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1. A memory cell comprising:
a substrate having a first doped region and a second doped region spaced apart from each other and defining a channel region therebetween;
a floating gate over the substrate, the floating gate overlapping the first doped region and the channel region, the floating gate including a first end disposed over the channel region and a second end opposite the first end disposed over the first doped region;
a control gate over the substrate, the control gate including a first portion arranged laterally adjacent to the second end of the floating gate and a second portion arranged over and overlapping the second end of the floating gate;
a word line over the substrate, a first end of the word line arranged over and overlapping the channel region and not overlapping the second doped region, a second end of the word line arranged over and overlapping the first end of the floating gate and the second portion the control gate;
a first insulation member on the substrate, the first insulation member separating the floating gate, the control gate and the word line from the substrate;
a second insulation member on the floating gate, the second insulation member separating the floating gate from the control gate; and
a third insulation member on the substrate, the floating gate and the control gate, a first portion of the third insulation member separating the floating gate and the control gate from the word line and a second portion of the third insulation member separating the word line from the second doped region,
wherein the substrate has a first conductivity type and the first and second doped regions have a second conductivity type opposite the first conductivity type.
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