US 12,324,151 B2
Semiconductor memory device and manufacturing method of semiconductor memory device
Nam Jae Lee, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on May 25, 2021, as Appl. No. 17/329,924.
Claims priority of application No. 10-2020-0154975 (KR), filed on Nov. 18, 2020.
Prior Publication US 2022/0157839 A1, May 19, 2022
Int. Cl. H10B 41/40 (2023.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); H10B 43/40 (2023.01)
CPC H10B 41/40 (2023.02) [H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/40 (2023.02)] 13 Claims
OG exemplary drawing
 
1. A semiconductor memory device comprising:
an insulating layer covering a peripheral circuit structure;
a contact structure connected to the peripheral circuit structure while penetrating the insulating layer, the contact structure including a protrusion part protruding farther than the insulating layer in a vertical direction opposite to a direction toward the peripheral circuit structure;
a first conductive line including a bending part surrounding the protrusion part of the contact structure and a horizontal part extending onto the insulating layer from the bending part, wherein the first conductive line further includes a first conductive metal barrier layer, a metal layer formed on the first conductive metal barrier layer, and a second conductive metal barrier layer formed on the metal layer;
a conductive bonding pad bonded to an upper surface of the bending part of the first conductive line; and
a memory structure connected to the conductive bonding pad,
wherein the metal layer of the first conductive line penetrates the second conductive metal barrier layer of the first conductive line, and is bonded to the conductive bonding pad.