US 12,324,148 B2
Method for forming semiconductor structure and a semiconductor
Chih-Cheng Liu, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Appl. No. 17/767,574
Filed by ChangXin Memory Technologies, Inc., Hefei (CN)
PCT Filed Aug. 16, 2021, PCT No. PCT/CN2021/112876
§ 371(c)(1), (2) Date Apr. 8, 2022,
PCT Pub. No. WO2022/134623, PCT Pub. Date Jun. 30, 2022.
Claims priority of application No. 202011552783.6 (CN), filed on Dec. 24, 2020.
Prior Publication US 2024/0268104 A1, Aug. 8, 2024
Int. Cl. H10B 12/00 (2023.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01)
CPC H10B 12/50 (2023.02) [H01L 21/7682 (2013.01); H01L 21/76837 (2013.01); H01L 23/5222 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A method for forming a semiconductor structure, including:
forming a plurality of discrete transistor structures on a substrate;
forming a dielectric layer covering the plurality of discrete transistor structures;
forming a plurality of metal lines on a top surface of the dielectric layer;
forming an opening in a gap between two of plurality of metal lines; and
filling the opening with an insulating layer;
wherein a dielectric constant of the insulating layer is smaller than a dielectric constant of the dielectric layer, and wherein the insulating layer reduced a parasitic capacitance among the plurality of metal lines and a parasitic capacitance between the plurality of metal lines and the plurality of discrete transistor structures; and
wherein a material of the insulating layer comprises silicon oxide doped with boron or phosphorus.