US 12,324,146 B2
Vertical DRAM structure and method of formation
Sai-Hooi Yeong, Zhubei (TW); Bo-Feng Young, Taipei (TW); and Chi On Chui, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on May 18, 2022, as Appl. No. 17/747,389.
Claims priority of provisional application 63/267,152, filed on Jan. 26, 2022.
Prior Publication US 2023/0240066 A1, Jul. 27, 2023
Int. Cl. H01L 21/00 (2006.01); G11C 5/06 (2006.01); H10B 12/00 (2023.01); H10D 64/27 (2025.01)
CPC H10B 12/395 (2023.02) [G11C 5/063 (2013.01); H10B 12/0383 (2023.02); H10B 12/0385 (2023.02); H10B 12/315 (2023.02); H10B 12/482 (2023.02); H10B 12/488 (2023.02); H10D 64/513 (2025.01)] 19 Claims
OG exemplary drawing
 
1. A method comprising:
depositing a first insulating layer over a substrate;
forming a bitline wiring in the first insulating layer, the bitline wiring having a first lengthwise direction;
depositing a semiconductor material layer over the first insulating layer;
patterning the semiconductor material layer into a plurality of pillars disposed along the bitline wiring;
depositing a gate dielectric layer over the pillars;
depositing a second insulating layer over the gate dielectric layer; and
forming a capacitor directly over each pillar of the plurality of pillars.