US 12,324,142 B2
Semiconductor device including write transistor and read transistor having read word line and read bit line at opposite ends of read channel layer
Mir Im, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on May 26, 2022, as Appl. No. 17/825,133.
Claims priority of application No. 10-2021-0138870 (KR), filed on Oct. 18, 2021.
Prior Publication US 2023/0122541 A1, Apr. 20, 2023
Int. Cl. H10B 12/00 (2023.01)
CPC H10B 12/20 (2023.02) [H10B 12/50 (2023.02)] 27 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a memory cell including a write transistor and a read transistor that are electrically connected to each other,
wherein the write transistor comprises:
a write bit line disposed over a substrate and extending in a direction parallel to a surface of the substrate;
a write channel structure disposed on the write bit line and extending in a direction perpendicular to the surface of the substrate;
a write gate dielectric layer disposed on a side surface of the write channel structure; and
a write word line disposed on the write gate dielectric layer, and
wherein the read transistor comprises:
a read gate electrode layer disposed on the write channel structure;
a read gate dielectric layer disposed on the read gate electrode layer;
a read channel layer disposed on the read gate dielectric layer; and
a read word line and a read bit line that are disposed at opposite ends of the read channel layer.