| CPC H04N 25/77 (2023.01) | 20 Claims |
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1. An image sensor comprising:
a pixel array including a plurality of pixels, wherein each of the plurality of pixels includes a first photodiode, a second photodiode, a first transfer gate, a second transfer gate, and a plurality of active regions; and
a logic circuit configured to control the plurality of pixels,
wherein each of a plurality of pixel groups in the pixel array includes a first pixel and a second pixel among the plurality of pixels, and the first pixel and the second pixel are adjacent to each other in a first direction,
wherein the plurality of active regions in each of the first pixel and the second pixel include a first active region and a second active region, wherein the first active region is adjacent to the first transfer gate, and the second active region is adjacent to the second transfer gate, and
wherein in each of the plurality of pixel groups, a plurality of source-follower transistors respectively has a gate connected to the first active region and the second active region of the first pixel and connected to the first active region and the second active region of the second pixel, wherein the plurality of source-follower transistors are disposed in the first pixel, and a plurality of switch transistors are disposed in the second pixel, and
in each of the plurality of pixel groups, a number of the plurality of source-follower transistors that are disposed in the first pixel is less than a number of the plurality of switch transistors that are disposed in the second pixel.
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