| CPC H04N 19/70 (2014.11) [H04N 19/105 (2014.11); H04N 19/172 (2014.11); H04N 19/174 (2014.11)] | 3 Claims |

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1. A device comprising one or more processors configured to:
decode a first syntax element in a sequence parameter set, wherein the first syntax element is a one bit flag and the first syntax element equal to a first value specifies that long term reference pictures might be used for inter prediction;
decode a reference picture list structure in the sequence parameter set;
decode a second syntax element in the reference picture list structure based on a value of the first syntax element, wherein the second syntax element is a one bit flag and the second syntax element specifies whether picture order count least significant bits of long term reference picture entries are present in the reference picture list structure;
decode a third syntax element in the reference picture list structure, wherein the third syntax element specifies a number of entries in the reference picture list structure; and
for each i-th entry in the reference picture list structure specified by a value of the third syntax element, decode a fourth syntax element in the reference picture list structure based on a value of the second syntax element, wherein the fourth syntax element specifies a value of a picture order count modulo of a picture referred to by an i-th entry in the reference picture list structure.
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