US 12,323,598 B2
Metering bits in video encoder to achieve targeted data rate and video quality level
Kannan Vairavan, San Mateo, CA (US); and Milan Mehta, San Mateo, CA (US)
Assigned to Sony Interactive Entertainment Inc., Tokyo (JP)
Filed by Sony Interactive Entertainment Inc., Tokyo (JP)
Filed on Oct. 18, 2022, as Appl. No. 18/047,621.
Prior Publication US 2024/0129486 A1, Apr. 18, 2024
Int. Cl. H04N 19/146 (2014.01); H04N 19/114 (2014.01); H04N 19/124 (2014.01)
CPC H04N 19/146 (2014.11) [H04N 19/114 (2014.11); H04N 19/124 (2014.11)] 18 Claims
OG exemplary drawing
 
1. An apparatus comprising:
at least one processor configured to:
maintain at least one video buffer according to a rate buffer bit controller feedback loop and a proportional integral derivative (PID) bit controller feedback loop, wherein the PID bit controller feedback loop comprises:
first, second, and third branches in parallel with each other and each receiving a feedback error, the first branch configured to correct a target bit rate based at least in part on the feedback error for a first term, the second branch configured to correct the target bit rate based at least in part on the feedback error for a second term longer than the first term, the third branch being configured to reduce overshoot;
use a predefined first quantization parameter (QP) for a first I frame of a group of pictures (GOP), the first I frame being an initial I frame of the GOP; and
use a second QP for a second I frame of the GOP, the second QP determined by the at least one processor from a third QP of a previous I frame in the GOP and a fourth QP of a last non-I frame of the GOP that preceded the second I frame.