US 12,323,504 B2
Clock correction method and clock correction circuit
Tien Ke Huang, Hsinchu (TW); and Chao-Yuan Hsu, Hsinchu (TW)
Assigned to Realtek Semiconductor Corporation, Hsinchu (TW)
Filed by Realtek Semiconductor Corporation, Hsinchu (TW)
Filed on Oct. 2, 2023, as Appl. No. 18/479,815.
Claims priority of application No. 112116860 (TW), filed on May 5, 2023.
Prior Publication US 2024/0372695 A1, Nov. 7, 2024
Int. Cl. H04L 7/00 (2006.01); H04B 17/20 (2015.01); H04L 7/033 (2006.01); H04L 25/00 (2006.01); H04L 25/40 (2006.01)
CPC H04L 7/0087 (2013.01) [H04B 17/204 (2023.05); H04L 7/0337 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A clock correction method, suitable for a communication device comprising a clock correction circuit, wherein the clock correction circuit is configured to receive a fast clock and a slow clock, the clock correction method comprises:
in response to the communication device being enabled and entering an active mode, calculating, by the clock correction circuit, a clock-period ratio between the slow clock and the fast clock;
in response to the communication device operating in a power-saving mode for a power-saving period, counting at least one rising edge of the slow clock received by the clock correction circuit during the power-saving period, as a cumulative number of slow clock periods;
in response to the communication device switching from the power-saving mode to the active mode, calculating the difference between an internal time of the communication device and a reference time of another communication device as a time offset; and
in the active mode, adjusting, by the clock correction circuit, the clock-period ratio by using a compensation value, wherein the compensation value is related to the clock-period ratio, the cumulative number of slow clock periods and the time offset.