| CPC H04L 67/568 (2022.05) [G06F 11/1464 (2013.01); G06F 11/1474 (2013.01); G06Q 40/04 (2013.01); H04L 12/00 (2013.01); H04L 67/55 (2022.05); G06F 2201/805 (2013.01); G06F 2201/84 (2013.01)] | 27 Claims |

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1. A system comprising:
a processor configured to:
store data received during an interval in a memory coupled with the processor, each received data indicative of an incremental change to a state of a data object, wherein the amount of data stored varies based on the number of incremental changes occurring during the interval at the end of which the data object is characterized by a new state resulting therefrom, a length of the interval varying based on an amount of time needed to encode the stored received data and an amount of time needed to transmit, via an electronic communications network, previously encoded data which was stored in the memory during a prior interval so that the encoding can be completed substantially proximate to the completion of the transmission; and
commence encoding, subsequent to the end of the interval, of the stored received data, such that the transmission thereof and encoding of subsequently stored data may commence thereafter.
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