| CPC H04L 5/0053 (2013.01) [H04W 72/0466 (2013.01)] | 12 Claims |

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1. A baseband processor comprising:
processing circuitry to:
receive configuration information from a base station, the configuration information to indicate at least two codewords are enabled for uplink transmissions;
receive scheduling information to schedule an uplink transmission;
identify a first mapping between a first phase-tracking reference signal (PTRS) port and a first transmission layer;
identify a second mapping between a first codeword and the first PTRS port; and
map the first codeword to the first transmission layer based on the first and second mappings;
map, based on the scheduling information and configuration information, a second codeword to a second transmission layer; and
generate the first codeword for transmission with the first transmission layer and the second codeword with the second transmission layer; and
interface circuitry coupled with the processing circuitry, the interface circuitry to enable communication.
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