US 12,323,163 B2
Low-density parity-check (LDPC) encoding method and apparatus
Guido Montorsi, Turin (IT); Sergio Benedetto, Turin (IT); Wei Lin, Shenzhen (CN); and Yan Xin, Ottawa (CA)
Assigned to Huawei Technologies Co., Ltd., Shenzhen (CN)
Filed by HUAWEI TECHNOLOGIES CO., LTD., Guangdong (CN)
Filed on Jan. 4, 2024, as Appl. No. 18/404,768.
Application 18/404,768 is a continuation of application No. 17/732,776, filed on Apr. 29, 2022, granted, now 11,901,914.
Application 17/732,776 is a continuation of application No. PCT/CN2020/125484, filed on Oct. 30, 2020.
Claims priority of application No. 201911047476.X (CN), filed on Nov. 21, 2022.
Prior Publication US 2024/0204800 A1, Jun. 20, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H03M 13/11 (2006.01); H03M 13/00 (2006.01)
CPC H03M 13/1157 (2013.01) [H03M 13/1151 (2013.01); H03M 13/616 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A chip, comprising:
at least one processor; and
one or more memories coupled to the at least one processor and storing programming instructions for execution by the at least one processor to cause a transmit end comprising the chip to:
obtain k information bits to be sent to a receive end;
perform low-density parity-check (LDPC) encoding on the k information bits by using a first check matrix based on a first transmission code rate R satisfying R=k/(n+j×Z) to obtain a first codeword; and
send the first codeword to the receive end, wherein:
k is an integer greater than 0;
the first check matrix is a submatrix of the first ((n−k)/Z+j) rows and the first (n/Z+j) columns in a check matrix H, and a code rate of the first check matrix is equal to the first transmission code rate;
n is an integer greater than 0, j is an integer greater than or equal to 0, and Z is an integer greater than 0;
the check matrix H is a matrix of ((n−k)/Z+Q) rows and (n/Z+Q) columns, Q is an integer greater than or equal to j, each element in the check matrix H represents one Z×Z square submatrix, and the square submatrix is a cyclic permutation matrix of an identity matrix or an all-zero matrix;
the check matrix H comprises a matrix HMC, a matrix HIR of Q rows and 24 columns, an all-zero matrix of 4 rows and Q columns, and an identity matrix of Q rows and Q columns; and
the matrix HMC is a matrix of (n −k)/Z rows and n/Z columns, the matrix HMC is located at an upper left corner of the check matrix H, the matrix HIR of Q rows and 24 columns is located at a lower left corner of the check matrix H, the all-zero matrix of 4 rows and Q columns is located at an upper right corner of the check matrix H, and the identity matrix of Q rows and Q columns is located at a lower right corner of the check matrix H; and
the first codeword comprises the k information bits and (n−k+j×Z) redundant bits.