US 12,323,156 B2
Clock signal generation circuit
LiJun Gu, Suzhou (CN)
Assigned to Realtek Semiconductor Corp., HsinChu (TW)
Filed by Realtek Semiconductor Corp., HsinChu (TW)
Filed on Oct. 18, 2022, as Appl. No. 17/968,791.
Claims priority of application No. 202111275517.8 (CN), filed on Oct. 29, 2021.
Prior Publication US 2023/0140495 A1, May 4, 2023
Int. Cl. H03L 7/22 (2006.01); G06F 1/12 (2006.01); G11C 7/22 (2006.01); H03L 7/08 (2006.01)
CPC H03L 7/22 (2013.01) [G06F 1/12 (2013.01); G11C 7/222 (2013.01); H03L 7/08 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A clock signal generation circuit, comprising:
a global phase-locked loop (PLL), configured to receives a reference clock signal to generate a synchronization clock signal; and
a plurality of local PLLs, wherein the plurality of local PLLs receive the synchronization clock signal to generate a plurality of clock signals, respectively, and the plurality of clock signals are used to generate a plurality of output clock signals;
wherein the plurality of local PLLs comprise at least a first local PLL and a second local PLL, the first local PLL is configured to receive the synchronization clock signal to generate at least one first clock signal for generating a plurality of first output clock signals; and the second local PLL receives the synchronization clock signal to generate at least one second clock signal for generating a plurality of second output clock signals;
wherein the clock signal generation circuit further comprises
a plurality of first phase adjustment circuits, configured to adjust phase(s) of the at least one first clock signal to generate the plurality of first output clock signals, respectively; and
a plurality of second phase adjustment circuits, configured to adjust phase(s) of the at least one second clock signal to generate the plurality of second output clock signals, respectively.