US 12,323,154 B2
Frequency detector and operating method thereof
Jahoon Jin, Suwon-si (KR); Sangho Kim, Suwon-si (KR); Kyunghwan Min, Suwon-si (KR); Soomin Lee, Suwon-si (KR); and Sodam Ju, Suwon-si (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Jul. 28, 2023, as Appl. No. 18/361,059.
Claims priority of application No. 10-2023-0018843 (KR), filed on Feb. 13, 2023.
Prior Publication US 2024/0275390 A1, Aug. 15, 2024
Int. Cl. H03L 7/091 (2006.01); H03L 7/081 (2006.01)
CPC H03L 7/091 (2013.01) [H03L 7/0816 (2013.01); H03L 2207/06 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A frequency detector, comprising:
a first flip-flop configured to generate a first signal by sampling a clock signal based on a data signal;
a second flip-flop configured to generate a second signal by (i) sampling a delayed-phase component of the clock signal based on the data signal or (ii) sampling the clock signal based on a delayed-phase component of the data signal;
a third flip-flop configured to generate a third signal based on the first signal and the second signal such that the third signal represents a polarity of a frequency difference between a data rate of the data signal and a frequency of the clock signal; and
a delay cell configured to generate the delayed-phase component of the clock signal or the delayed-phase component of the data signal such that a delay amount thereof is less than 0.25 Unit Interval (UI).